Published on November 11, 2016 by IEEE Computer Society

Optimizing processors for (a) specific application(s) can substantially improve energy-efficiency. With the end of Dennard
scaling, and the corresponding reduction in energy-efficiency gains from technology scaling, such approaches may become
increasingly important. However, designing application-specific processors requires fast design space exploration tools to optimize for
the targeted application(s). Analytical models can be a good fit for such design space exploration as they provide fast performance and
power estimates and insight into the interaction between an application’s characteristics and the micro-architecture of a processor.
Unfortunately, prior analytical models for superscalar out-of-order processors require micro-architecture dependent inputs, such as
cache miss rates, branch miss rates and memory-level parallelism. This requires profiling the applications for each cache and branch
predictor configuration of interest, which is far more time-consuming than evaluating the analytical performance models. In this work we
present a micro-architecture independent profiler and associated analytical models that allow us to produce performance and power
estimates across a large superscalar out-of-order processor design space almost instantaneously.

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